As LED manufacturers relentlessly strive to produce greater light output at a lower cost, the most significant advance in cost per lumen in recent years has been the adoption of patterned sapphire substrates (PSS).
When a pattern is etched onto polished sapphire — the material used as a substrate in the vast majority of LED chips — total light extraction efficiency (LEE) can be increased by as much as 30 percent. This can happen in two different ways:
(1) By encouraging lateral growth of the epitaxial layers, thereby reducing epitaxial defect density and increasing the light emission of the active quantum well layers
(2) By reducing light loss, through creation of a photon scattering effect that allows more of the light generated to escape
Generally, the patterns consist of shapes — cones, domes, pyramids — created in a hexagonal pattern on the surface of the sapphire through dry plasma etching. Pattern features may be 0.65 to 2 microns in height, and the pitch (the distance between the centers of adjacent features) may be 1.5 to 3 microns.
These pattern designs are developed independently by each of the LED manufacturers to meet the needs of their unique epitaxial recipes and are considered proprietary technology. Because of this, no standard library of patterns exists. The critical dimensions to increasing LEE include the shape and size of the pattern features and the aspect ratio — the ratio of height to width. Deeper patterns tend to be associated with greater LEE, but can be difficult to make if conditions are not well-controlled.
In addition to developing their PSS recipes in-house, LED manufacturers originally performed the patterning operations themselves. While most still conduct some of their patterning operations in-house, third-party patterning became more available in 2010 for two-inch wafers, and later four-inch wafers. It was then that LED companies had the option of outsourcing at least a portion of their patterning activity.
Concurrently with the development of patterned wafers, LED chip manufacturers have been slowly migrating to larger substrates for greater efficiency. Larger wafers provide several benefits, including:
- Increased throughput for each reactor run, effectively increasing capacity without adding additional MOCVD reactors or additional floor space
- Reduced edge loss
- Reduced wafer handling
The yield for PSS at larger diameters is affected by the flatness of the wafer, and bowing of the wafer can cause inconsistent etching and lower yields.
So what’s next for PSS? Can we get even more luminous efficiency with this technology?
Nanoscale patterning has been extensively studied for its potential impact on light extraction efficiency due to both its significantly increased pattern density and its impact on internal quantum efficiency from the improvement of epitaxial quality. As we continue to test new patterns and sizes, like nanoscale patterning, it is clear that the industry hasn’t reached a wall in what is possible for light output. Further advances in PSS technology will provide improvements in light extraction efficiency, contributing to the continued market success of LED technology.